ΨΗΦΙΑΚΗ ΣΧΕΔΙΑΣΗ
Έγγραφα
Τύπος | Aρχείο ![]() | Μέγεθος | Ημερομηνία | |
---|---|---|---|---|
Lab 10: Verilog (Μέρος 5 - FSM) | 1.36 MB | 16/1/24 | ||
Lab 10: Sequential Circuits - FSM | 4.6 MB | 8/1/24 | ||
Lab 09: Flip-Flops | 1.32 MB | 18/12/23 | ||
Lab 08: Verilog (Μέρος 4) | 777.04 KB | 11/12/23 | ||
Lab 08: Latches and Sequential Logic Circuits | 1.51 MB | 11/12/23 | ||
Lab 05: Visual Studio Code | 1.16 MB | 5/12/23 | ||
Lab 05: Binary Conversion and Adders | 1.65 MB | 5/12/23 | ||
Lab 04: Verilog (Μέρος 3) | 2.32 MB | 27/11/23 | ||
Lab 04: Karnaugh Maps | 1.1 MB | 27/11/23 | ||
Lab 04: Icarus Verilog & GTKWave | 1.65 MB | 27/11/23 | ||
Lab 03: Verilog (Μέρος 2) | 1.9 MB | 23/11/23 | ||
Lab 03: Logic Gates Explored and Boolean Algebra | 2.2 MB | 14/11/23 | ||
Lab 02: Verilog Icarus | 2.44 MB | 7/11/23 | ||
Lab 02: Verilog (Μέρος 1) | 2.04 MB | 7/11/23 | ||
Lab 02: Truth Tables and Basic Logic Gates | 1.14 MB | 8/11/23 | ||
Lab 01: Multisim installation | 1.82 MB | 30/10/23 | ||
Lab 01: Multisim Circuit Simulation and Basic Gates | 2.64 MB | 30/10/23 | ||
Intro | 1.71 MB | 24/10/23 |